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Viterbi Encoder / Decoder IP Core

SeaSolve’s Viterbi Decoder is a parameterizable high performance IP core that performs decoding of the convolutionally encoded data as well as punctured codes. The core is compatible with various standards such as DVB, 3G, WLAN, WIMAX IEEE 802.16d and 802.16e. This low latency decoder core supports various code rates, constraint lengths and generator polynomials and supports soft decision decoding.The core offers wireless Chipset designers, OEM’s and ODM’s a standard compliant platform to accelerate development process and reduce time to market.


For additional information and licensing of the IP core please contact: info@seasolve.com

Dot Standards supported : DVB, 3G and IEEE 802.11 a/b/g
Dot Selectable code rates 1/2, 2/3, 3/4
Dot Parameterizable trace backs depth of 35 to 105 for punctured data
Dot Parameterizable constraint length up to 7
Dot Generator polynomials (G0 =1338,G1 = 1718)
Dot De puncturing of punctured convolutional encoded data
Dot Parameterizable generator polynomials
Dot Hard Decision Decoding
Dot Supports standards such as IEEE 802.11a/b/g and DVB
Dot VHDL simulation model
Dot Flexible architecture suitable for FPGA or ASIC
Dot Provide standard interface with external devices

Encoder Pin Diagram

Convolutional Encoder Block Diagram Viterbi Decoder Block Diagram
Dot Fully Synthesizable VHDL code
Dot Fully Functional Test bench
Dot Timing simulated target specific VHDL code
Dot Design flow documentation
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