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CTC Encoder/Decoder

SeaSolve’s Mobile WiMAX CTC decoder Core performs duo binary turbo decoding of channel data as per IEEE 802.16e/d specification. The decoder uses MAX LOG MAP Algorithm for decoding.

The CTC decoder is capable of achieving a high throughput encode data rate in the slowest speed FPGA also.


For additional information and licensing of the IP core please contact: info@seasolve.com

Dot Fully synthesizable code
Dot Supports all interleaver block sizes of the CTC OFDMA PHY mode including the HARQ and IR HARQ modes: 24, 36, 48, 72, 96,108, 120, 144, 180, 192, 216, 240, 480, 960, 1440, 1920, and 2400 pairs.
Dot Programmable number of iterations dynamically changeable per block
Dot Performs parallel processing with parameterizable number of SISOs to achieve high throughput and reduce latency Latency depends on block size
clk in std_logic;
rst in std_logic;
new_block is a pulse;
no_iter is a 3 bit input which reads 0 to 7
n_size takes the size of the input
a input a
b input a
y1 input a
w1 input a
y2 input a
w2 input a
new_data is a valid_out
hard_bits output data
finished is a done signal





The Core is delivered as a synthesized netlist (FPGA) or RTL VHDL for ASIC. The Core package contains:

Dot RTL-model library for simulation (ModelSim)
Dot Stand-alone test bench (VHDL)
Dot Complete documentation and technical support for integration
IP Cores Resource