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Advanced Encryption Standard IP core

AES IP core is designed with ultimate flexibility which lets the core to support variable key and data block sizes. It is programmable for 128, 192 and 256 bit key lengths. It supports various cipher modes- ECB, CBC, and OCB with or without key scheduler/expander.

SeaSolve’s AES IP core is simple to use, highly flexible and can be easily integrated into any AES design requirement. The fully functional synchronous core is available in Source or Netlist forms.

Functional Description

SeaSolve’s AES IP core implements the 128-bit block-size NIST FIPS AES algorithm. The encryption core accepts a 128-bit plain text input data, and generates a corresponding 128-bit cipher text output data using a given 128, 192, or 256-bit AES key. The decryption core provides the opposite function, generating plaintext from supplied cipher text, using the same AES key as was used for encryption.


For additional information and licensing of the IP core please contact: info@seasolve.com

Dot Complaint with the latest released Publication 197 from NIST™
Dot Supports operating Modes like ECB, CBC, and OCB with or without key scheduler/expander
Dot Full Dynamic support for all Key size of 128, 192 and 256 bits
Dot Supports Data blocks of 128, 192 and 256 bits
Dot Fully synchronous design
Dot Verified using software simulations
Dot Different gate count/speed combinations
Dot Authentication (OCB Mode)
Dot Protected network routersDeliverables include Test benches
Dot Synthesizable VHDL RTL source code
Dot Netlist for Xilinx and Altera FPGA devices
Dot Highly optimized C source Code
Dot Self-checking test benches
Dot Test Vectors
Dot Comprehensive Documentation
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